The present invention relates generally to a semiconductor device and method for manufacturing the same. More particularly, a semiconductor device using an extremely thin silicon on insulator (ETSOI) substrate and method for manufacturing the same.
Semiconductor technology is employed in almost every electronic circuit application. One type of semiconductor technology employs Silicon-On-Insulator (SOI) substrates in place of conventional silicon. The benefit of SOI over conventional silicon is the reduced parasitic capacitance that leads to improved performance. The implementation of SOI technology has allowed for the continued scaling planar silicon technology.
Extremely Thin Silicon-On-Insulator (ETSOI) is a leading candidate for further continued scaling of planar silicon technology. However, a concern with fabricating the ETSOI is creating a shallow trench isolation. The shallow trench isolation is a trench that is formed from a top material layer on a wafer to a buried oxide layer and is then filled with an electrically-insulative material such as oxide to separate two devices. During the middle-of-the-line processing (MOL) applications, contacts are put onto the contact points of the semiconductor device.
However, during MOL applications, contacts can be misaligned and touch the top of the shallow trench isolation region, which would create a short circuit and render the device useless. A short circuit occurs when there is an abnormally low-resistance connection betweens two nodes of an electrical circuit that are meant to be at different voltages. Because of the lack of electrical insulation, this creates an undesirable condition such as damage or overheating of the semiconductor. This scenario is illustrated in FIG. 1.
FIG. 1 shows a conventional transistor that has a substrate including a substrate layer (100′), a BOX layer (200′), a silicon on insulator (SOI) layer (300′) and a shallow trench isolation (700′). As shown in the figure, the contacts (1000′) are either partially or fully in the shallow trench isolation which causes the short circuit, rendering the device completely useless.
The proposed method and apparatus incorporates a liner into the BOX that will limit the recess of the oxide layers during etching and also prevent a short from occurring during MOL applications.